Error Control Coding (ECC) schemes are essential in data storage applications to provide data integrity. Reliability of storage systems such as NAND flash memories may decline as higher storage density is achieved with multi-level cell (MLC)/triple-level cell (TLC) technologies. Different ECC schemes can be used to detect and correct the errors and improve the reliability of these systems. The ECC codes may include low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo product codes (TPCs), and the like.
TPC codes are a promising ECC candidate for storage applications. TPC decoding is usually performed by iteratively decoding one or more of the constituent codewords in a TPC code. In general, TPC decoder could provide better hardware complexity and power consumption performance than LDPC decoder. However, for applications in which the TPC decoder is required to support multiple code rates, hardware complexity of the TPC decoder increases. In an LDPC decoder, most of the hardware blocks can be reused to support different code rates. However, TPC decoders are usually customized for a specific code rate. In conventional systems, in order to support different TPC code rates, several hardware components are duplicated and customized for each code rate. There is a need in the art for low complexity TPC decoders that support multiple code rates.